An Efficient Sequence to Apply Slicing Lines in Fpga Placement

One of the steps involved in the computer-aided design for FPGA (FieldProgrammable Gate Array) circuits is placement. In this step, the logic functions are assigned to specific cells of the circuit. In conventional hierarchical min-cut based placement algorithms, the layout region is bi-partitioned using slicing lines in a top-down manner. In these placement algorithms, the cut-line is always chosen at the center of the current region. In this paper we propose another sequence of slicing lines which reduces the maximum cut size and the total wirelength of the circuit.